Tutorial T11: Design of Energy and Area Efficient Circuits Using Spin Devices in Combination with CMOS

CMOS technology has been facing enormous challenges at the moment and these challenges will grow further in the future. It is, therefore, prudent to explore alternative technologies to sustain the famous Moore's law far in the future. Most of the Electronics even today is based on the movement of charges which is highly inefficient in terms of power consumption. Spin is also a very fundamental property like charge of carriers which has been ignored till recently. Spin based devices which exploit this property for computation has emerged very recently as a promising technology with a potential to complement MOS or to replace it altogether in the post-CMOS era. The biggest advantage of these spintronic devices is that their form factor is comparable to MOS technology and are realized in interconnect layers without any real Si area overhead. Recent experiments have shown that a spin polarized current can switch the state of magnetization of a nano-magnet by spin transfer torque mechanism. Most of the spintronic devices are based on this mechanism. It is possible to design energy and area efficient circuits by the combination of spintronic devices and CMOS. This tutorial will concentrate on the design of logic and memory circuits using the combination of CMOS and spintronic devices by exploiting their unique characteristics of nonvolatile storage with no Si area overhead.