System Verilog Assertions Synthesis Based Compiler

This paper presents an architecture of system Verilog assertions (SVA) synthesis compiler, which translates the un-synthesizable System Verilog assertions, into synthesizable equivalent Verilog modules, in order to convert them to digital hardware circuits, used to watch how the running design performs. The proposed architecture is based on two main rules: "Simple compiler structure" and "generic implementation". The reason behind why assertions synthesis is a good idea, is that these synthesized assertions can be used in order to localize errors if they exist, so debugging process becomes more efficient, faster, and also, it gives a full visibility of the running design on FPGA, which makes design prototyping based verification - especially for SoCs - more efficient, accurate in recognizing bugs, and tell precisely, why system failures occur. Also, assertions hardware checkers can be used to keep eyes on the performance of critical FPGA-based applications. Therefore, resources utilization was a very important aspect to be considered in order to maintain area effectiveness as most as possible.