FPGA implementation of multichannel satellite modulator: An efficient data buffering technique

This paper discusses the design and successful implementation of a packet based Multichannel satellite modulator using efficient, novel Data buffering technique. The modulator receives data from IP network and transmits it to satellite network. The scheme allows for loss-less transfer of data from Best effort IP based packet network to a circuit switched fixed bit rate narrow band continuous satellite modulator. The multichannel scalable modulator is implemented in Xilinx Virtex-6 FPGA. The IP packet processed in another device reaches FPGA via EMIF interface as RAW chunk of data of multiple channels, which are further processed and buffered using a novel low latency scheme. The buffered data is serialized and modulated. The modulation chain incorporates [1] INTEL-SAT V.35 Scrabmbler, Differential encoder, 1/2 rate convolutional encoder, RRC filtering and employs BPSK modulation.