Network on chip simulator: Design, implementation and comparison of Mesh, Torus and RiCoBiT topologies

The introduction of billions of transisters onto a single chip has resulted in the increase in complexity of the common System-on-Chip(SoC) architecture. The bus based architecture of SoC is limiting, mainly due to scalability issues. The solution for this communication problem is the use of embedded switching network, called Network On Chip(NoC). NoC has inherent redundancy which helps to tolerate faults and deal with communication bottleneck. In this paper we discuss about the design and implementation of different Network On Chip (NOC) based topologies. The topologies that we consider here are 2D Mesh, Torus and RiCoBiT. This paper compares the performance parameters of the above three topologies and thus it would help the network designers to design a high performance system.