Laser Pooling: Static and Dynamic Laser Power Allocation for On-Chip Optical Interconnects

The advent of many-core processors with hundreds of processing cores collocated on single silicon dies requires scalable and efficient on-chip interconnects. Research suggests conventional electrical interconnects will be inadequate to support large-scale many-core processors. Thus, emerging technologies such as on-chip silicon nanophotonics may help meet the demands of future many-core processors by providing high-bandwidth and low-power communication over extended distances. Nanophotonic interconnects require a large external laser source which is often wasted during periods of low network utilization. We propose laser pooling techniques, where we share laser power among all the nodes and effectively share the link bandwidth and power. Furthermore, we design both static and dynamic techniques to scale laser power with network load. Evaluation and simulations of the proposed architecture estimate the proposed architecture, powering 16 optical channels with 0.5 dB/cm waveguide cladding losses, would require only 5.1 W of laser power versus 12.3 W of laser power for the baseline architecture, almost 58.5% laser power savings, while incurring only a 22% saturation throughput penalty.