Design of an op-amp as a Comparator of 10 bit Split SAR ADC using Cadence tool

This paper presents designing of an op-amp of 10 bit SAR (Successive Approximation Register) ADC with Split DAC structure for medium resolution. Op-amp as an Comparator circuit is designed and simulated using gpdk (generic process design kit) 180 nm process technology in Cadence Virtuoso tool and simulation results for 30MHZ are power dissipation = 282.262μWatt, Gain at 1.6V = 43.54dB, Unity Gain Bandwidth = 27.315 MHz and Offset Voltage = 67.5975nV.