Analysis and design of low power nonlinear PFD architectures for a fast locking PLL

Two novel nonlinear phase frequency detectors (NL-PFD1 and NL-PFD2) designed with the objective of achieving higher gain, eliminating blind zone, reducing dead zone and area are proposed in this paper. Using pass transistor logic in realizing D-flip-flop has resulted in higher gain, area reduction and higher maximum frequency for NL-PFD2. Reset delay and dead zone are also found to be reduced using simple structure. The necessity of reset action is eliminated in both the NL-PFDs as UP and DN signals are never allowed to reach logic high simultaneously and hence, blind zone is completely eliminated in both the cases. Nonlinear Phase-Voltage characteristics of PFD has been modeled using Fourier series and time response of PLL using state space technique and both have been validated by simulation in MATLAB and circuit simulation in Cadence. PLL built with the NL-PFDs are found to provide a lock time of 1.753 μs and reference spur of -56.7 dBc with 180 nm CMOS process while power dissipation in NL-PFD2 is observed to be only 0.27μW.