Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect

This paper describes the integration of copper and SilK in a 0.18 /spl mu/m DLM interconnect. The main integration issues such as dual damascene patterning, SilK porosity and copper filling have been addressed, as shown by the 0.5 /spl Omega/-100% yield obtained for 0.3 /spl mu/m vias. The Cu/SilK interest is confirmed by a 40% RC reduction compared to a Cu-SiO/sub 2/ structure.