26.4 A 0.4-to-1V 1MHz-to-2GHz switched-capacitor adiabatic clock driver achieving 55.6% clock power reduction

Clock distribution in modern SoCs consumes a significant fraction of total chip power. To reduce clock distribution power, resonant clocking schemes, where an inductive reactance is used to cancel the capacitive reactance of global clock networks at a given resonance frequency, f
_o
, have been proposed. Conventionally, such schemes are only suitable at high multi-GHz frequencies in order to be able to place the employed inductors on chip [1, 2]. Since many modern energy-efficient SoC designs optimize for clock frequencies <;2GHz, with DVFS techniques bringing the core clock frequencies and the supply voltages V
_DD
to the MHz and near-threshold regimes, respectively, there is a need to develop low-power clock distribution schemes that can work across increasingly wider operating ranges. Recent work in quasi-continuous resonant clocking has proposed intermittent cancelation of global clock-tree capacitance during edge transitions, however, such techniques require large off-chip inductors and are limited to 0.98MHz [3] and 150MHz [4], respectively, owing to the need to operate well below resonance (i.e., <; f
_o
/10). Thus, while prior-art has shown power reduction for targeted applications, they all require large on- or off-chip magnetics, and do not meet the MHz-to-GHz frequency-range needs of modern DVFS-enabled SoCs. To address these problems, this paper introduces a fully integrated adiabatic clocking scheme that efficiently synthesizes n-step clock waveforms from 1MHz to 2GHz via a switched-capacitor DC-AC multi-level inverter topology, theoretically reducing power by 1/n without using any magnetic component.