20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control

Low-dropout regulators (LDOs) are widely distributed in SoC designs to supply individual voltage domains, and a digital LDO (DLDO) is favorable for its low-voltage operation and process scalability. However, as many SoCs generate a load current (I
_LOAD
) variation at sub-A/ns level, voltage regulators require a large area-consuming output capacitor (C
_OUT
) to maintain the output voltage (V
_OUT
) during fast transients. A conventional shift-register (SR)-based DLDO [1] suffers from a power and speed trade-off, thus requires a large C
_OUT
. To break the tie and minimize C
_OUT
, [2-5] applied coarse-fine tuning and adaptive clocking, but a fast sampling clock is still necessary for instantaneous V
_OUT
sensing. Event-driven control used in [6] reacts fast within one clock cycle, but the ADC (with 7 comparators) and the digital PI controller increase the complexity and power consumption. This work presents an analog-assisted (AA) tri-loop control scheme for transient improvement, low power, and C
_OUT
reduction.