19.4 A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving −236.2dB jitter-FOM

High-performance phase-locked loops (PLLs) and clock multipliers with low jitter/phase noise are essential for numerous applications, such as digital microprocessors and SoCs, wireline/optical links, data converters and wireless radios. Given the increasing cost per unit area of advanced CMOS nodes and the need for a multitude of PLLs in complex digital systems, there is a need to miniaturize the area of PLLs while not sacrificing jitter and phase noise performance. Ring oscillators are extremely compact when compared with their LC counterparts, but exhibit typically 15-to-20dB worse phase noise performance. A conventional analog charge-pump PLL that exploits a passive loop filter can be low-noise but requires a large loop-filter capacitor for frequency compensation, which dominates the area in a ring-oscillator PLL. An analog sub-sampling PLL [1] dramatically lowers in-band phase noise, but requires an even larger loop-filter capacitor to achieve comparable loop dynamics unless pulsing is employed [1,2]. Digital PLLs are extremely compact but are plagued by quantization-noise and deterministic-jitter issues. Active loop filters can substantially lower the area requirements as well, but are associated with severe linearity and (phase) noise penalties, which are further exacerbated as CMOS technology scales. A time-based proportional-integral-controlled (PI-controlled) active loop filter was presented in [3] that uses a current-controlled ring oscillator (CCRO) as an ideal integrator, addressing linearity and DC gain challenges, but the loop filter noise results in a jitter Figure-of-Merit (FOM) that is >10dB inferior to state-of-the-art ring-oscillator PLLs.