Dual-mode double precision division architecture

This paper presents an area efficient architecture for a dual-mode double precision floating point division, which can either process a double precision (DP) division or two parallel single precision (SP) division. The dual-mode mantissa division architecture is based on the series expansion methodology, and implemented in an iterative fashion. A dual-mode Radix-4 Modified Booth multiplier is designed for this purpose, which is used iteratively in the architecture of dual-mode mantissa computation. The proposed dual-mode division architecture is synthesized using UMC 90nm technology ASIC implementation. The proposed architecture shows better design metrics in terms of required area, time-period and throughput as against prior literature work.