FinFET MPSoC 32 Gb/s transceivers: Custom ESD protection and verification

Custom ESD protection without increasing loading capacitance is demonstrated for transmitter (TX) and receiver (RX) pins of the Xilinx Zynq UltraScale+ Microprocessor System-on-Chip (MPSoC) transceivers. Optimized T-coil cancellation was applied at a 32 Gb/s bit rate. Fast and reliable verification of the custom ESD design was developed based on Calibre PERC schematic checking combined with Calibre DRC design rule checking. Our proposed analytical model shows ~50% increase of the electric field at the FinFET top compared to planar sidewalls. A higher electric field at the fin-top decreases gate oxide breakdown, reduces RX charged device model (CDM) immunity for the FinFET MPSoC, and brings the RX on par with the TX, CDM-wise.