A feasible scheduling algorithm for per-VC queueing ATM switches

This paper introduces a scheduling algorithm for per-VC queueing ATM switches. Our proposed per-VC queueing scheduler (PVQS) achieves a low maximum delay, provides bandwidth guarantee, and fairly allocates excess capacity. The computation in PVQS is carried out on a per-connection basis, not on a per-cell basis which is mandatory in the virtual time-stamp type of approach. This leads to a significant reduction in computational effort and makes PVQS a feasible candidate for practical implementation in per-VC queueing ATM switches.