A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS

This paper presents the design and implementation of a 10-bit ultra-low voltage energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). The proposed first 2-bit guess (F2G) scheme reduces the DAC switching energy by 90% and improves the DNL and INL by √(3/2) in theory compared with the conventional approach. By employing majority-vote comparison at the conversions of LSBs, the noise requirement of comparator can be relaxed by half. With the segmented and bundled routing, the parasitic capacitors of bottom-plates of DAC array are reduced to improve power efficiency and speed. Implemented in 90-nm CMOS technology, the test chip occupied a core area of 0.03 mm
²
. The prototype consumes 67.3 nW at 150 kS/s from a single 0.3 V supply voltage and achieves an ENOB of 8.85 bits and an SFDR of 70.7 dB at Nyquist input, respectively. The resultant Walden's FoM and Schreier's FoM are 0.97 fJ/conv.-step and 175.5 dB, respectively.