Thermal stress reliability of copper through silicon via interconnects for 3D logic devices

For 3D-LSI devices using the through silicon via (TSV) process, there are many reliability issues regarding the large thermal-mechanical stress and deformation volume changes caused by mismatch of the thermal expansion coefficients (CTEs) between the Cu and Si substrate in the device active area. In this paper, we investigated the TSV leakage current in metal-insulator-semiconductors and studies MOSFET device characteristics to manage manufacturing quality based on stress propagation of Cu-TSVs by thermal loading in the operating temperature range (-50 to 80 °C) and relatively high process temperature range (250 to 400 °C). The stress induced leakage current and MOSFET mobility change showed a relationship between expansion and contraction deformation of Cu under the thermal loading conditions. These results show that Cu/Si interface formation quality is high although there is major TSV metallization. Furthermore, it was found that precise estimation is important to designing the keep out zone (KOZ) in consideration of the real operating temperature.