Array pass transistor design in trench cell for Gbit DRAM and beyond

Aggressive scaling of the DRAM cell size requires minimum dimensions in both the channel length and the channel width of the array pass transistor. As a result of the stringent leakage current requirement, the design for the array MOSFET becomes increasingly challenging as cell size is reduced. In this paper, we present data that illustrate the importance of the channel and the source/drain engineering, along with considerations of minimizing the junction leakage. By utilizing a 512 k array diagnostic monitor, a methodology is presented for optimum array cell design in a statistically reliable manner. Design issues unique to the trench capacitor cell are covered. Alternative biasing schemes that boost the process window are also discussed.