A fast-acquisition demodulation scheme for 2.4 GHz wireless DSSS transceiver VLSI

In this paper, a CMOS cell based system VLSI design for Direct-Sequence Spread-Spectrum (DSSS) wireless LAN transceiver is presented. In addition, an efficient and fast-acquisition demodulation scheme is proposed to use in the receiver architecture. Implementation and testing results are also given. The proposed demodulation scheme can help to positively combine the received signal energy of multipaths so that the detection performance is improved by 3 dB in a typical frequency-selective indoor wireless communication environment. The proposed architecture can synchronize the PN code in 30 /spl mu/s and the chip size is 5600/spl times/4600 /spl mu/m/sup 2/. It can be operated from 3.3 V to 5 V and the power consumption ranges from 189 mW to 250 mW respectively.