Sensitivity of a 10nm dual-gate GAA Si nanowire nMOSFET to process variation

Advances in technology has allowed us to demand for high speed and low power devices in modern chips. These transistors are scaled down and examined with multi-gate architecture in order to improve electrostatic control over the channel and reduce power consumption. A novel dual-gate gate-all-around (GAA) junctionless nanowire transistor (JNT) is addressed in this work. Using TCAD device modeling, we report a process variability analysis and explored the device characteristics. A cylindrical nanowire with a channel length of 10 nm and a diameter of 5 nm is employed to study the process sensitivity of the device. A 1 nm thick HfO2 gate is used as a dielectric material. Analysis from deep depletion to strong accumulation mode with a 2e19 cm
^-3
n-type channel doping (Vds = 0.8V and T = 300 K) is reported. The dual-gate GAA JNT shows an improved electrical behavior with a variation to channel doping, channel diameter, channel length and oxide thickness. It also has an enhanced short channel behavior such as high Ion/Ioff (>10
⁶
), good sub threshold slope (~68 mV/decade) and low drain induced barrier lowering (~8mV/V) compared to conventional inversion mode transistors and regular nanowire GAA devices that makes the device a candidate for energy efficiency improvements.