Implementation of FM0/Manchester encoding using SOLS technique for DSRC application

DSRC (Dedicated Short Range Communication) is an emerging technique that permits very high data transmission critical in communications-based active safety applications. DSRC standards usually adopt either FM0 code or Manchester code as a coding technique to enhance signal reliability, to reach dc balance. The codeword structure of FM0 and Manchester are different, thus limiting the hardware potential of existing DSRC systems. Similarity oriented logic simplification (SOLS) techniques merges hardware architectures of both FM0 and Manchester and integrated architecture gives better hardware utilization rate (HUR). The performance of this paper is validated on Xilinx ISE design suite 14.7. We have implemented the SOLS design at transistor level with 0.18-μm CMOS technology using mentor graphics tools.