A system level integration methodology for MPEG-2 audio decoder with embedded RISC core

MPEG2 audio decoding algorithms are involved of several complex-coding techniques and therefore difficult to do efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG2 audio decoder. The MPEG2 audio algorithms can be roughly divided into two types of operations. Based on standard cell design technique, the chip size is 6.4/spl times/6.4 mm/sup 2/, and the tested chip can run at maximum 43.5 MHz clock rate.