Tuning of Multiple Parameters With a BIST System

This paper presents a low-power built-in self-test system to compensate for mismatch and variations in CMOS IC. The system is designed and compiled on a low-power field programmable analog array (FPAA) fabricated on a 350-nm CMOS process. A second-order bandpass filter is used as a device under test. A set of 12 parallel filter banks are compiled on three different FPAA chips and compensated for local mismatch and variations in the bias current, and mismatch in parasitic and routing capacitances. The bandpass filters are biased in subthreshold regime and the system of 12 parallel filter banks consumes a power of 7.072 μW. The proposed tuning algorithm reduces variation in center frequency to 5.07% compared with a variation of 10.16% when they are not tuned, variation in quality factor to 8.52% from 13.86%, and variation in the gain at the center frequency to 3.83% from 21.04%. These values are deviation of the parameters from its mean for the data taken from three different FPAA chips fabricated on the same wafer.