Static power reduction in caches using deterministic naps

We propose a technique that reduces static power consumption in caches with negligible hardware overhead and no performance penalties. Our proposed architecture achieves this by deterministically lowering the power state of cache lines that are guaranteed not to be accessed in the immediate future by exploiting in-flight cache access information. We simulated our architecture using the Simple scalar and Cacti toolsets, and observed up to 92% reduction in static power consumption in SPEC2006 benchmarks with no performance penalties and minimal hardware overhead.