Compensation for inverter nonlinearity considering voltage drops and switching delays of each leg's switches

This paper proposes a compensation method for inverter nonlinearity for an accurate voltage synthesis. The inverter nonlinearity is caused by dead-times, voltage drops and switching delays and parasitic output capacitance of semiconductor switches, and propagation delays in the gate drive circuits. This paper regards dead-times, voltage drops and switching delays of semiconductor switches as dominant voltage distortion factors. Analyzing those factors of each leg, the proposed method compensates nonlinearity of each leg of inverters. As a result, accurate voltages can be synthesized. Experimental results verify the effectiveness of the proposed method.