Short Channel Effects suppression in a dual-gate Gate-All-Around Si nanowire junctionless nMOSFET

Advances in short channel transistor technology has allowed the emergence of these devices in modern chips. These transistors experience many different types of Short Channel Effects (SCE) that are addressed in this work. Using TCAD simulations, we report a new and effective technique to reduce SCE in a novel dual-gate silicon nanowire Gate-All-Around (GAA) junctionless transistor. A channel length of 10 nm and a diameter of 5 nm is employed to mitigate SCE in terms of Subthreshold Slope (SS), Leakage current (Ioff) and Drain Induced Barrier Lowering (DIBL). A 1 nm thick HfO
₂
gate is used as a dielectric material. Analysis from deep depletion to strong accumulation mode with 2e19 cm
^-3
n-type channel doping (Vds = 0.8V and T = 300 K) is reported. The dual-gate GAA junctionless nanowire transistor shows improved electrical characteristics such as high Ion/Ioff (>10
⁶
), good subthreshold slope (~68 mV/decade) and low drain induced barrier lowering (~8 mV/V) compared to conventional inversion mode transistors and single nanowire GAA devices that makes the device a candidate for energy efficiency improvements.