Efficient methodology for testable reversible sequential circuit design

Due to ultra-low power consumption, demand of reversible logic has been increased. In this article, primary intention is to not to increase the garbage output, area and delay to introduce testable feature in reversible sequential circuit. By this proposed approach without changing the existing design, testable feature is easily introduced at reversible latch. Introducing testable feature into the reversible latch without changing the existing design is being proposed for first time to literature. Designing the testable reversible sequential circuit with such few garbage output, quantum cost and delay was not introduced before.