Acceleration of genetic algorithm based FPGA placers using GPGPU

With the scaling of process nodes, the complexity of IC design continues to increase. This increase in complexity greatly increases the time needed by many electronic design automation (EDA) tools to perform optimizations. Placer is one such tool that has been seeing a large increase in the time required for execution. Due to the large solution space and tight constraints, the amount of computations needed to arrive at a reasonably good solution increases exponentially. This work explores the acceleration of a genetic algorithm-based placer for field programmable gate arrays (FPGAs) using general-purpose computing on graphics processing units (GPGPUs).