Performance of Zero forcing pre-coder for vectored DSL

This paper deal with the performance analysis of vectored DSL in terms of the computational complexity and practical implementation on DSP processor. Paper is more specific for the design of diagonalizing pre-coder in downstream transmission of vectored DSL. Different algorithms for the design of linear and nonlinear pre-coders have been proposed in the past. All of these pre-coders are either highly complex in design or they give poor performance in terms of bit rate. As the cost of the customer premises modem is an important issue, any technique that can minimize the complexity of the system is extremely beneficial. In this paper performance in terms of execution time for basic model and diagonalizing pre-coder of vectored DSL is been analyzed using DSK 6713 a digital signal 32 bit, floating point processor. The clock frequency of mention processor is considered as 250 MHz. This processor has advanced very long instruction word (VLIW) architecture, with performance of up-to 2400 (532) million instructions per second. The execution time of the processor is compared with the Matlab profiler function.