A concurrent approach to detect and diagnose shorts in interconnects of on-chip networks

Different system level failures such as packet duplication and misrouting due to short faults in NoC interconnects have become a burden for reliable communication. Furthermore, the failure mode is extended to packet dropping that enhances packet timeout fault. As a result, interconnect shorts significantly affect various performance metrics. This paper presents a new model that tests shorts on NoC interconnects and accounts the impact of these faults on performance metrics. The 4-corner principle is introduced to accelerate the proposed test application. The model is scalable with all meshes and tori by default. Simulation results demonstrate an effectiveness of the model and provide the impact of interconnect shorts on NoC performances.