A high-throughput multi-match priority encoder for data retrieval on 65-nm SOTB CMOS process

In this paper, a high-throughput multi-match priority encoder (MPE) for data retrieval is implemented in a low-power 65-nm SOTB CMOS process. This approach employs an 8-bit priority encoder (PE) as a basement and utilizes a new design architecture to construct a 2,048-bit MPE (MPE2K). The experimental results on an FPGA proved that the operating frequency of MPE2K is 1.42 times higher than that of similar design, while the resource utilization is 4.39 times lower. Moreover, when being applied in a 100-MHz data analytics system, MPE2K achieves the minimum throughput of 99.8 Mbps. The post-simulation results on SOTB process indicate that MPE2K can operate at 312 MHz and consumes 9.56 mW at 1.0 V. Additionally, at 0.4 V, the leakage current in idle mode is reduced approximately 203.8 times due to the usage of reverse body bias voltage.