Optimal design of full subtractor using Particle Swarm Optimization with Aging Leader and Challenger algorithm

As the VLSI technology grows up, optimization is required to reduce the complexity, area and power of the digital circuits. In order to optimize the hardware requirement of digital combinational circuits, evolutionary techniques need to be enforced at various levels such as gate level and device level. This paper presents an efficient approach for the optimal design of a combinational logic circuit with a reduced gate count in MATLAB platform. The evolutionary optimization technique used is Particle Swarm Optimization with Aging Leader and Challenger (ALC-PSO). The results obtained after optimization of Full Subtractor circuit using ALC-PSO technique are shown to have a less number of gates compared to human design method. Later on that optimized circuit has been analysed by DSCH3.5 and Microwind3.1 VLSI CAD Tool. The results shown in this paper reflects that technology scaling decreases the area, delay and power consumption which are some of the major requirements of today's VLSI design.