Testing of memristor ratioed logic (MRL) XOR gate

This paper focuses on the production testing of Memristor Ratioed Logic (MRL) XOR gate. MRL is a family that uses memristors along with CMOS inverters to design logic gates. The two-input MRL XOR gate is investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. It is shown that faults in the XOR gate produce analog output voltage values because of the circuit architecture. Therefore, a 2-bit Flash ADC is used as a special test equipment to achieve full fault coverage. Finally, four resistive short faults in the XOR gate can only be detected by monitoring the input current. It is shown that exhaustive testing is needed in order to obtain 100% fault coverage.