Experimental and Simulation Study of Silicon Nanowire Transistors Using Heavily Doped Channels

The experimental results from 8 nm diameter silicon nanowire junctionless field-effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/μm for 1.0 V and 2.52 mA/μm for 1.8 V gate overdrive with an off-current set at 100 nA/μm. On- to off-current ratios above 10
⁸
with a subthreshold slope of 66 mV/dec are demonstrated at 25 °C. Simulations using drift-diffusion which include density-gradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength.