Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors

This paper describes design challenge in 3D NAND technology and proposes an area- and power-efficient 20V charge pump using multiple tiers for pump capacitors. Using 32 tiers, the pump area and power are respectively reduced by a factor of 4.8 and 1.3 compared to a conventional N-well capacitor pump in 2.5V 3D NAND technology without adding any extra process cost. Charge pump design strategy is also discussed. The operation frequency can be reduced by a factor of two as the number of tiers is doubled, which further improves power efficiency as 3D NAND technology is advanced.