The Bel array: An asynchronous fine-grained co-processor for DSP

This paper analyses the Bit-Element (Bel) Array, a fine-grained (single-bit) asynchronous reconfigurable 2D array designed using NULL Convention Logic (NCL) set up as a coprocessor for Digital Signal Processing (DSP) applications. Each Bel can perform a limited number of two-input Boolean gate functions, inversion, routing or produce 1-bit constant values. This fine grained reconfigurable fabric exhibits spatial computing characteristics that can provide massive parallelism within and across micro-pipelines. NCL implementation enables operation over a broad voltage range to suit (slower) low power operation, or low latency and high performance (higher power). An example DSP application, a single-bit Delta Sigma 20-tap Short Word Length (SWL) Finite Impulse Response (FIR) filter is used to illustrate the mapping and configuration process, occupying an effective area less than 0.164 square millimeters on a 28 nm process.