Many-thread aware instruction-level parallelism: Architecting shader cores for GPU computing

The design philosophy of many-core architectures such as graphics processing units (GPUs) is to exploit thread-level parallelism (TLP) to achieve high throughput. Compared to central processing unit (CPU) designs, GPU-like many-core architectures spend the on-die area mainly for computational/instruction execution logic rather than caches or complex instruction processing, such as register renaming and out-of-order execution, to extract instruction-level parallelism (ILP). Each core in a GPU, referred to as a shader core (SC), is a relatively simple in-order multi-threaded processor, which relies on TLP to overcome pipeline hazards. In this paper, we propose to architect SCs for GPU-like many-core processors to achieve both high performance and high energyand area-efficiency.