Programmable incrementing/decrementing binary accumulator for high-speed calibration loops

In this paper a structure for high-speed incrementing/decrementing accumulator is proposed based on even and odd unit cells. Step of accumulation can be chosen among ±2
ⁿ
levels where n = 0, 1, 2, 3, ... through a control digital word. A 10-bit accumulator is divided into two 5-bit accumulators where each one is realized in carry-ripple adder/subtractor structure. Basic cells are highly improved in number of logic gates and propagation delay and carry-select technique is employed for the higher 5-bit accumulator to further boost the correction speed in any digital calibration loops. Simulation results confirm that the proposed accumulator can operate with the step of ±2
ⁿ
, 0 ≤ n ≤ 4, in either incrementing and decrementing directions at 1.4GS/s update rate. Power consumption reaches to 960μW at 1.8Volts supply voltage. Simulations are performed at all process corners using the standard 0.18μm CMOS technology.