Low-latency lossless compression using dual-stream coding

Lossless compression in data-bus systems and storage devices will be effective to improve the performance of data intensive computings which require high-throughput data transfers between components, e.g., processing nodes, memory modules, and storage devices. For such applications, the latency and throughput of codec will be important factors as well as the compression ratio. This paper proposes a low-latency high-throughput compression algorithm suitable for hardware implementation. The algorithm has two coding streams, namely, differential-word and parameter-word codings, which can be executed in parallel. A naive codec is designed using Verilog-HDL, and implementation results show that the complexity and throughput are comparable to conventional low-latency compression algorithms. The compression ratio is evaluated by computer simulation, and the results show that the proposed algorithm has superior compression ratios compared to the conventional algorithm.