Si-passivated Ge nMOS gate stack with low Dit and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal

We demonstrate a Si-passivated Ge nMOS gate stack with D
_IT
of ~5×10
¹⁰
cm
^-2
eV
^-1
around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of ~1×10
⁸
cm
^-2
at V
_ov
/CET=3.5 MV/cm). Insertion of a 3D-compatible thin ALD LaO
_x
, MgO
_x
and LaSiO layer at the interface between HfO
₂
and SiO
₂
/Si/Ge improves PBTI reliability thanks to the interface dipole-induced band engineering. The high D
_IT
of Si-passivated Ge nFET is dramatically reduced by ~40x around midgap using a combination of the LaSiO insertion and a H
₂
high-pressure anneal (HPA). These key gate stack technologies realize further improvements in mobility (~50% at peak) and PBTI reliability (V
_ov
=0.32 V for 10 years) of Si-passivated Ge nFETs.