Charge Trapping Analysis of Metal/Al2O3/SiO2/Si, Gate Stack for Emerging Embedded Memories

For Al
₂
O
₃
charge trapping analysis, Metal/Al
₂
O
₃
/SiO
₂
/Si (MAOS) structures are fabricated from atomic layer deposition and plasma enhanced chemical vapor deposition-based Al
₂
O
₃
and SiO
₂
thin films, respectively. The fabricated MAOS devices showed high memory window of ~7.81V@16V sweep voltage and leakage current density of ~3.88 × 10
^-6
A/cm
²
@-1V. The charge trapping and decay mechanism are investigated with the variation of alumina thickness by Kelvin probe force microscopy (KPFM). It reveals that vertical charge decay is a dominant phenomenon of charge loss for Al
₂
O
₃
in contrast to lateral charge spreading. Constant current stress (CCS) measurements mark the location of charge trap centroid at ~10.30 nm from metal/Al
₂
O
₃
interface attributes that bulk traps present close to the Al
₂
O
₃
/SiO
₂
interface are dominant charge trap centres. In addition, a simple method is proposed to estimate the trap density using KPFM and CCS method at room temperature. Furthermore, there is ~28% exponential decay in high state capacitance observed after 10
⁴
s in capacitance-time analysis at room temperature. This material engineering of charge traps will improve the performance and functionality of bilayer Al
₂
O
₃
/SiO
₂
structure for embedded memory applications.