A new bank sensitive DRAMPower model for efficient design space exploration

In systems ranging from mobile devices to servers, Dynamic Random Access Memories (DRAM) have a large impact on performance and contribute a significant part to the total consumed power. Therefore, it is crucial to have an accurate DRAM power model for exhaustive design space explorations, which can handle different types of DRAM devices. In this paper, we present an improved version of the well known DRAMPower model. Our enhanced model is derived and calibrated from real measurements and outperforms pessimistic state-of-the-art DRAM power estimators like the widely used spread sheet provided by Micron.