A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects

Modern digital designs, beyond adopting measures for energy-, area-efficiency and performance, have to adopt additional measures for a more robust functionality throughout their lifetime. On the way to finding cost-effective resilience approaches, an important first step is to analyze the system behavior in the presence of errors. This gives insight to the system designers regarding the criticality of the system nodes and, so, more targeted and efficient measures can be applied. However, given the complexity of modern systems and the abundance of potential vulnerable parts, typical approaches that perform such analysis rely on system simulation and lack scalability. Alternative solutions are required that go beyond the traditional, time-consuming simulation experiments. This paper proposes a framework to handle in a scalable way error injection and propagation through linear time invariant blocks in presence of finite wordlength effects.