TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs

In the nano scale era, the upcoming design challenges like dark silicon, power wall, and memory wall have prompted extensive research into the architectural alternatives to the general purpose processor. Coarse Grained Reconfig-urable Architectures (CGRAs) are emerging as one of the promising alternatives. Commonly, CGRAs are composed of a computation layer and a memory layer. Tempted by higher platform utilization and energy efficiency, recently proposed CGRAs offer dynamic remapping and parallelism. However, the existing works only address the computational elements, while for many applications the bulk of energy is consumed by the memory and memory accesses. Therefore, without architectural support to optimize the memory contents, according to the changes in computational layer, the benefits promised by dynamic parallelism and remapping are severely degraded. As a solution to this problem we present TransMem, a supporting memory infrastructure that complements the dynamic remapping and parallelism in the computational fabric. Simulation results reveal that the additional flexibility enhances the energy efficiency by up to 85% for the tested applications, compared to state of the art. Post-layout analysis reveals that TransMem incurs only 4% area penalty.