Negative Capacitance for Boosting Tunnel FET performance

We have proposed and investigated a super steep subthreshold slope transistor by introducing negative capacitance of a ferroelectric HfO
₂
gate insulator to a vertical tunnel FET for energy efficient computing. The channel structure and gate insulator are systematically designed to maximize the I
_on
/I
_off
ratio. The simulation study reveals that the electric field at the tunnel junction can be effectively enhanced by potential amplification due to the negative capacitance. The enhanced electric field increases the band-to-band tunneling rate and I
_on
/I
_off
ratio, which results in 10× higher energy efficiency than in tunnel FET.