An Efficient Approach Targeting Broken Topological Clock Path for Master — Generated Clock Pair

Constraint management plays a crucial role in ASIC design development. Acting as directives to the STA tool, constraints set up an environment in order to analyse the design for various timing issues. However, due to their mismanagement, serious design complications creep in and tend to hamper the system functionality on the whole. One of the important and fundamental challenge relates to the unavailability of the timing path between the master clock and its derivative (known as generated clock). This issue, if not addressed, renders the design analysis incomplete thereby resulting in functional defects getting introduced into the design. This paper highlights and addresses the issue by presenting an algorithm that captures the instances of broken topological paths and reports the specific reason. It further attempts to identify the overlapping reasons which get unnoticed by current state of the art methodologies. It further modifies the clock-specific constraints in order to resolve the problem without impacting the design functionality. Experimental results on set top box chip show the effectiveness and the efficiency of this method.