A low power current sensing scheme for cmos sram

A low power current sensing scheme for CMOS SRAM is presented in this paper. The proposed scheme includes a modified current conveyor as the column selector, and a new designed low power current sense amplifier to sense the small differential current signals in data lines. The output of the sense amplifier is fed to a clock control RS latch both for power reduction and longer output valid time. This current sensing scheme is clocked asynchronously and the timing control circuits are also discussed. Simulation results show that a sensing speed with 3ns less is achieved by this scheme and the sensing speed is insensitive to both bit line and data line capacitances.