Simulating a pipelined RISC processor

Most of the processors available now days have a pipelined architecture. The pipelined processors are designed in a way that they can process more than one instructions in the same clock pulse. To achieve this phenomenon of multiple processing, the processors are designed to have multiple stages. These stages work together as single unit under common clock pulse to generate the effect of multiple processing. Generally we have Instruction fetch, Instruction decode, Execution, Memory and Write back stages in a five stage pipelined RISC processor. Each of these stages works as a sub processor connected in the sequence. Such that with every clock pulse each of them process one instruction and forwards it to the next stage in the sequence. To understand the implementation of these concepts, in this paper we have materialized a working simulation of a pipelined RISC processor.