A high throughput architecture of DCTQ processor suitable for FPGA implementation utilizing Fox algorithm

The Discrete Cosine Transform (DCT) is a standard in the media industry for video and image compression techniques like MPEG2 and JPEG. Even though the Discrete Wavelet Transform (DWT) performs better, DCT computation is faster which entails its use in real time applications. This is especially useful in the internet of things era which require real time processing. As such, it is required to efficiently and swiftly compute the DCT output for which FPGAs prove to be indispensable. Exploiting the use of massive parallelism in an FPGA, we can increase the throughput as well as speed. To achieve this, a novel architecture for the efficient and swift computation of DCT is proposed consisting of 83 pipeline stages and achieving a maximum clock speed of 156.424 MHz simulated in Xilinx ISE Design Suite 13.2 with Spartan 3E as the target FPGA.