Study on the latency efficient IFFT design method for low latency communication systems

In this paper, we propose latency efficient Inverse Fast Fourier Transform (IFFT) design method reducing the latency of IFFT output through the reordering of IFFT input data from the resource element mapper to IFFT input signal. The IFFT core consumes a significant percentage for high speed communication systems such as Long Term Evolution (LTE). So, IFFT processor in the physical layer implementations of baseband modem which is important component since IFFT processors require large amount of area and processing power. Also, IFFT has quite long latency from IFFT input data to output data. Therefore latency efficient IFFT is needed for providing various applications such as real time service without latency. Proposed IFFT architecture reduces IFFT output data delay through the reduction of IFFT memory size and butterfly operation (e.g. addition / subtraction). Third Generation Partnership Project - Long Term Evolution (3GPP - LTE) systems use 2048-point FFT processor in the 20MHz bandwidth. Thus, input signal of the IFFT processor corresponding to guard band are assigned as null (‘0’). Based on the fact that there are many null as an input signals of IFFT, a hardware and latency efficient IFFT design method for low latency communication systems like 5G LTE is proposed. To verify the performance of the proposed algorithm, 2048 point FFT with radix-2 based SDF structure is used.