Low power and noise resistant 16×16 SRAM array design using CMOS logic and differential sense amplifier

The main aim of this paper is to design a low power and noise resistant SRAM using Cadence (version 6.1.5) simulation tool. Standard gpdk180 library (i.e., 180nm technology node) is used for designing. A 16×16 SRAM array is designed having SRAM cells along with all peripheral components. Due to increased use of portable devices, power consumption has become an important parameter to be considered for efficient device design. Thus there is an urgent need of low power efficient memory design. This paper utilizes Full CMOS logic for SRAM cell design to effectively reduce static power dissipation as compared to resistive load inverter being used in previous designs. Peripheral components such as row decoder, precharge circuit, write driver circuit, sense amplifier and column decoder has been designed and assembled to form SRAM array. Differential type sense amplifier is used for noise reduction as it has the ability of common mode noise voltage rejection. Supply voltage of 1.8 V is considered. Transient responses for read and write operations for both logic-1 and logic-0 have been analyzed. Power consumption of 24.58 mW is measured for complete SRAM array.